System Level ESD Co-design and IC Level ESD Protection Measures

June 29, 2015 9:00 AM - 5:00 PM

June 30, 2015 9:00 AM - 1:00 PM

Instructors: Charvaka Duvvury, ESD Consulting LLC 
Harald Gossner, Intel Mobile Communications
 

The seminar offers a comprehensive view of on chip and on board ESD 
protection. Following the presentation of an essential on-chip protection 
methodology for ESD-robust component ICs, the Seminar will explain in 
detail the strategies for system level protection. These will include the 
methods and parameters which allow the system designer to achieve a fast solution for an ESD-robust system. This two-stage presentation allows the ESD engineer and the system designers to mutually understand and appropriately addresses the system ESD. To achieve these objectives the focus will be on the needs of system design engineers, PCB protection component suppliers and IC providers.

The course is divided into 4 parts:

1. IC level and system level ESD threats in real world and test methods for robustness qualification
2. Essentials of IC level ESD protection influencing system ESD behavior and the concept of system efficient ESD design (SEED)
3. System level ESD Codesign approach following the SEED concept
4. Analysis of soft fails and their mitigation strategies

The seminar is taught by Dr. Charvaka Duvvury (TI Fellow emeritus) and Dr. Harald Gossner (Intel Senior Principal Engineer) and is to a large extent based on the book 'System Level ESD Codesign' by Duvvury, Gossner, John Wiley, July 2015.

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