ESD Device Design Essentials
May 7-8, 2015
Instructors: Gianluca Boselli, Texas Instruments;
Michael G. Khazhinsky, Silicon Laboratories
This two-day seminar consists of concentrated versions of twelve ESDA
tutorials which comprise the ESDA Device Design Certification Program.
*ESD On-Chip Protection in Advanced Technologies
*SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits
*EOS/ESD Failure Models and Mechanisms
*On-Chip ESD Protection in RF Technologies
*Charged Device Model Phenomena and Design
*Latch-up Physics and Design
*Circuit Modeling and Simulation for On-Chip Protection
*Troubleshooting On-Chip ESD Failures
*Device Testing--IC Component Level: HBM, CDM, MM, and TLP
*Impact of Technology Scaling on ESD High Current Phenomena and Implications for Robust ESD Design
*Transmission Line Pulse Measurements: Parametric Analyzer for ESD On-Chip Protection
*System Level ESD/EMI: Testing to IEC and other Standards
DAY 1
PART I (8:00 AM-Noon)
This part reviews the fundamentals of ESD testing, high-current physics, and ESD modeling. The focus is on device-level (HBM, CDM, MM, TLP) and system level testing, impact of technology scaling on ESD high current phenomena, as well as circuit modeling and simulation for on-chip protection.
PART II (1:00 PM-5:00)
The principles from part I are then applied to ESD Protection Design. This part describes ESD on-chip protection in advanced technologies, SPICE-based ESD protection design utilizing diodes, and active MOSFET rail clamp circuits.
DAY 2
PART III (8:00 AM-Noon)
This part describes special ESD design cases, including Charged Device Model (CDM) phenomena and design, on-chip ESD protection in RF Technologies, and latch-up physics and design.
PART IV (1:00 PM-5:00)
The final section discusses EOS/ESD failure models and mechanisms. The seminar concludes with practical examples for troubleshooting of on-chip ESD failures.
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